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Half-adder gate from XOR and AND

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Exercise

https://texercises.com/exercise/half-adder-gate-from-xor-and-and/

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Exercise:
A half-adder takes two singlbit inputs A and B and produces two outputs: A S which is the least significant bit of the result and a carry C which is the carry-out bit. The S is if A and B are different and if they are the same. The carry is if both A and B are and otherwise. Construct a half-adder circuit using only textttXOR and textttAND gates. Draw the circuit diagram for your half-adder.

Solution:
center circuitikzscale. % XOR gate for Sum draw nodexor port xor ; nodeanchoreast at xor.in A; nodeanchoreast at xor.in B; nodeanchorwest at xor.out S Sum; % AND gate for Carry draw - nodeand port and ; nodeanchoreast at and.in A; nodeanchoreast at and.in B; nodeanchorwest at and.out C Carry; circuitikz center array|c|c|c|c| hline textInput A & textInput B & textSum S & textCarry C hline & & & & & & & & & & & & hline array

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Digitalelektronik 1 by uz

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Attributes & Decorations

Tags	algebra, and, bool, bool'sche, chip, circuit, computer, digital, digitalelektronik, elektronik, gate, logik, logische, not, or, schaltelement, schaltung
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Difficulty	(3, default)
Points	5 (default)
Language	(English)
Type	Calculative / Quantity
Creator	uz
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