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https://texercises.com/exercise/single-bit-storage-gate/
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Exercise:
An SR latch is a gate that stores a single bit of information. This gate has two inputs S set and R reset and two outputs Q and bar Q. The gates behaves as follows: If S and R the latch retains its state if S and R the latch sets Q and therefore bar Q if S and R the latch sets Q and therefore bar Q. The state S and R is invalid. Construct such an SR latch using only two textttNAND gates.

Solution:
center circuitikzscale. % NAND gates draw nodenand port nand ; draw nodenand port nand ; % Inputs nodeanchoreast at nand.in S; nodeanchoreast at nand.in R; % Outputs nodeanchorwest at nand.out Q; nodeanchorwest at nand.out overlineQ; % Connections draw nand.out |- ++. -| nand.in ; draw nand.out |- ++-. -| nand.in ; circuitikz center array|c|c|c|c| hline S & R & Q_textnext & overlineQ_textnext hline & & Q_textprev & overlineQ_textprev & & & & & & & & textInvalid & textInvalid hline array
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Exercise:
An SR latch is a gate that stores a single bit of information. This gate has two inputs S set and R reset and two outputs Q and bar Q. The gates behaves as follows: If S and R the latch retains its state if S and R the latch sets Q and therefore bar Q if S and R the latch sets Q and therefore bar Q. The state S and R is invalid. Construct such an SR latch using only two textttNAND gates.

Solution:
center circuitikzscale. % NAND gates draw nodenand port nand ; draw nodenand port nand ; % Inputs nodeanchoreast at nand.in S; nodeanchoreast at nand.in R; % Outputs nodeanchorwest at nand.out Q; nodeanchorwest at nand.out overlineQ; % Connections draw nand.out |- ++. -| nand.in ; draw nand.out |- ++-. -| nand.in ; circuitikz center array|c|c|c|c| hline S & R & Q_textnext & overlineQ_textnext hline & & Q_textprev & overlineQ_textprev & & & & & & & & textInvalid & textInvalid hline array
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Tags
digitalelektronik, elektronik, gate, latch, physik, sr, storage
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Difficulty
(1, default)
Points
2 (default)
Language
ENG (English)
Type
Calculative / Quantity
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